1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device.
2. Description of the Related Art
A conventionally known element separation method for a high voltage integrated circuit (HVIC) utilizes a high voltage junction in which a high potential side region and a low potential side region provided on a single semiconductor chip are electrically separated by a high-voltage junction termination region (HVJT) provided between the regions. It is known that a high-voltage n-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET: insulated gate field effect transistor) or a p-channel MOSFET functioning as a level shifter is arranged in the HVJT to transmit signals between a high potential region and a low potential region via the level shifter (see, e.g., Japanese Laid-Open Patent Publication Nos. H9-283716 and 2005-123512). Configurations of an HVJT and a level shifter of a conventional semiconductor device will be described.
FIGS. 20, 21, 22, 23, and 24 are plan views of examples of planar layouts of main parts of conventional semiconductor devices. FIGS. 20 and 21 are FIGS. 1 and 8, respectively, of Japanese Laid-Open Patent Publication No. H9-283716, and FIG. 24 is FIG. 6 of Japanese Laid-Open Patent Publication No. 2005-123512. The conventional semiconductor device depicted in FIG. 20 has a configuration including a high potential side region 211 and a low potential side region 212 on a single p−-type semiconductor substrate 201 with an HVJT 213 electrically separating the regions from each other. The high potential side region 211 is an n-type region 202 provided in the p−-type semiconductor substrate 201. The HVJT 213 is an n−-type region 203 surrounding a periphery of the n-type region 202. The low potential side region 212 is a portion of the p−-type semiconductor substrate 201 on the outer side than the n−-type region 203. In the n-type region 202 and the n−-type region 203, a portion (hereinafter referred to as a p−-type separation region) 204 of the p−-type semiconductor substrate 201 is interposed in a substantially U-shaped planar layout extending from the low potential side region 212 through the HVJT 213 and the high potential side region 211 and returning to the low potential side region 212.
The p−-type separation region 204 electrically separates portions 202a, 203a of continuous portions of the n-type region 202 and the n−-type region 203 from the other potions. An n-channel MOSFET used as a level shifter 214 is arranged in the portions 202a, 203a surrounded by the p−-type separation region 204. In the conventional semiconductor device depicted in FIG. 21, a p−-type separation region 205 arranged in a substantially rectangular frame-shaped planar layout in the n-type region 202 separates a portion (hereinafter referred to as a peripheral edge portion) 202b outside the n-type region 202 and a portion (hereinafter referred to as a central portion) inside the n-type region 202. An n-channel MOSFET used as the level shifter 214 is arranged continuously in the peripheral edge portion 202b of the n-type region 202 and the n−-type region 203. The arrangement of the high potential side region 211, the low potential side region 212, and the HVJT 213 of the conventional semiconductor device depicted in FIG. 21 is similar to that of the conventional semiconductor device depicted in FIG. 20 (similarly in FIGS. 22 to 24).
In the conventional semiconductor device depicted in FIG. 22, a p−-type separation region 206 arranged in a substantially C-shaped planar layout in the n-type region 202 separates a portion 202c extending along three sides of a peripheral edge portion of the n-type region 202 arranged in a rectangular planar layout and a central portion of the n-type region 202. An n-channel MOSFET used as the level shifter 214 is arranged continuously in the portion 202c extending along the three sides separated by the p−-type separation region 206 in the peripheral edge portion of the n-type region 202 and the n−-type region 203. A portion 202d extending along one side not separated by the p−-type separation region 206 in the peripheral edge portion of the n-type region 202 is fixed at the highest potential of the high potential side region 211. A resistance used as a level shift resistor is that of a diffusion region between the portion 202d fixed at the highest potential of the high potential side region 211 in the peripheral edge portion of the n-type region 202 and a drain region (not depicted) of the n-channel MOSFET constituting the level shifter 214.
The conventional semiconductor device depicted in FIG. 23 has a configuration in which a double Reduced Surface Field (RESURF) structure is applied to the HVJT 213 of the conventional semiconductor device depicted in FIG. 22. The double RESURF structure is made up of p-type regions 209a, 209b arranged in n−-type region 203. A p-channel MOSFET 214b used as the level shifter 214 is arranged continuously in the portion 202d fixed at the highest potential of the high potential side region 211 in the peripheral edge portion of the n-type region 202 and the n−-type region 203. The HVJT 213 and the low potential side region 212 are separated by a p−-type separation region 208. Reference numerals 221 to 224 denote a p-type base region, an n+-type source region, an n+-type drain region, and a gate electrode, respectively, of an n-channel MOSFET 214a constituting the level shifter 214. Reference numerals 225 to 227 denote a p+-type source region, a p+-type drain region, and a gate electrode, respectively, of the p-channel MOSFET 214b. An n+-type region 228 and a p+-type region 229 also serve as a cathode contact region and an anode contact region, respectively, of a parasitic diode of the HVJT 213.
In the conventional semiconductor device depicted in FIG. 24, a portion of the HVJT 213 is separated (e.g., at two positions) by a trench 207, and an n-channel MOSFET and a p-channel MOSFET used as the level shifters 214 (214a, 214b) are arranged in respective regions surrounded by the trench 207. Reference numerals 215, 216 are wires. As described above, in the configurations in which a portion of the HVJT 213 is used as the level shifter 214 depicted in FIGS. 20 to 24, the p−-type separation regions 204 to 206 or the trench 207 electrically separate a region of the high potential side region 211 in which an internal circuit is arranged and a region of the HVJT 213 in which at least the n-channel MOSFET used as the level shifter 214 is arranged. Additionally, the configurations need no high potential wiring passing over the HVJT 213 from the low potential side region 212 to the high potential side region 211 and therefore, are highly reliable. As compared to a configuration in which the level shifter 214 is arranged in a region other than the HVJT 213, the chip size can be reduced (shrunk) by the occupied area of the level shifter 214.